This invention relates to a picture processing apparatus. More particularly, this invention is directed to a picture processing apparatus for performing convolution processing on plural items of pixel data stored in a frame memory, on a time-sharing basis using a predetermined coefficient matrix comprising rows and colums.
For such purposes as sharpening a picture, removing background noise from a picture, etc., conventional practice is to perform convolution processing on pixel data in a frame memory using a predetermined weighted coefficient matrix comprising rows and columns.
FIG. 4(a) illustrates a coefficient matrix of five rows and five columns, and FIG. 4(b) illustrates 256.times.256 items of pixel data A.sub.11, A.sub.12, . . . , A.sub.256256 in a frame memory. Weighted coefficients C.sub.11, C.sub.12, . . . , C.sub.55 in the coefficient matrix have weighted values for attaining the aforementioned purposes.
In order to perform convolutioon processing with regard to the pixel data in a frame memory of the kind shown in FIG. 4(b) with a coefficient matrix of the kind shown in FIG. 4(a), a convolution processor is used. With a conventional processor, partial convolution processing is performed with regard to one predetermined row of pixel data in the frame memory. The results of this intermediatre processing are stored in a buffer RAM. Next, the intermediate results just stored in the buffer RAM are read out, and added to the results of the next partial convolution processing obtained from the convolution processor. The resulting sum is repeatedly stored at the address in the buffer RAM where the preceding intermediate processing results were stored, and the sum is read out from this address. Thus, convolution processing is performed on a time-sharing basis.
With the 5.times.5 coefficient matrix of the kind shown in FIG. 4(a), for example, this time-sharing convolution processing is executed by being split into five stages. When the convolution processing is performed with respect to the third row of pixel data in FIG. 4(b), partial convolution processing is carried out between the first row of the coefficient matrix and the first through 256 columns of pixel data in the first row in the first stage of processing. As shown in FIG. 6, ##EQU1## is stored in third through 254th columns of the first row of the buffer RAM as the respective intermediate processing results of the convolution processing. At this time, invalid data (indicated by the symbol "*" in the drawings) enter the first, second, 255th and 256th columns. Next, in the second stage of processing, the intermediate processing results stored in the buffer RAM are read out and, at the same time, the convolution processor performs partial convolution processing between the second row of the coefficient matrix and the first through 256th columns of pixel data in the second row. These partial results and the preceding intermediate processing results stored in a data latch circuit are added and the new intermediate processing results obtained from the addition are stored by rewriting the preceding intermediate processing results in the third through 254th columns of the buffer RAM, as shown in FIG. 6(b), at a write timing controlled by a bus buffer. Thus, ##EQU2## are written in the third through 254th columns of the buffer RAM.
The third, fourth and fifth stages of processing are executed through this procedure to store intermediate processing results of the kind shown in FIGS. 6(c), (d) and (e) in the first row of the buffer RAM. When the fifth stage of processing is performed, 5.times.5 matrix convolution processing with respect to the third row of the frame memory will be completed, so that results of the kind shown in FIG. 6(e) can be obtained. In other words, ##EQU3##
However, when the high-speed processing is attempted with this convolution apparatus for performing convolution processing on a time-sharing basis, a prescribed period of time is required for reading the intermediate processing results from the buffer RAM to the data latch circuit and for adding the intermediate processing results stored in the latch data circuit and the next convolution processing results from the convolution processor. Accordingly, a problem arises in that there is inadequate time for writing the intermediate processing results data in the buffer RAM.
For example, as shown in the timing chart of FIG. 5, if convolution processing is performed on one row of pixel data in the frame memory of FIG. 5(a), a time T, or a processing frequency f, needed for one partial convolution processing performed by the convolution processor will be a video rate of 167 ns, as shown in FIG. 5(b). In other words, the processing will be executed at 6 MHz. Therefore, it is necessary that the contents of the buffer RAM be read R and written W at this rate.
Though a buffer RAM capable of operating at high speed is used, the access time is 50 ns with C-MOS-type RAMs that are presently available.
FIG. 5(b) ilustrates the timing at which the first stage of convolution processing results are written (W) in the buffer RAM, and FIG. 5(c) shows the second stage of timing at which the intermediate processing results stored in the buffer RAM in the first stage of processing are read (R) and the sum obtained by adding these results to the next processing results are written (W) in the buffer RAM. It will be understood from FIGS. 5(c) and (d) that after the intermediate processing results stored in the buffer RAM in accordance with the first stage of processing are read (R) and stored in the data latch circuit, the timing for outputting the results from the latch circuit to the adder is delayed a predetermined period of time.
FIG. 5(e) illustrates the output of processing results at the next processing cycle of the convolution processor. FIG. 5(f) illustrates the timing for adding the results obtained in the next processing cycle of the convolution processor and the output from the data latch circuit shown in FIG. 5(d). The hatched portion indicates that the output of the adder is not valid. The timing at which the results of addition obtained from the adder are written in the buffer RAM is shown in FIG. 5(g). This is done by bus buffer on/off control and a buffer RAM write-enable signal. It will be understood from FIGS. 5(f) and (g) that since the results of addition obtained from the adder are considerably delayed with respect to the timing at which these results are written in the buffer RAM, the intermediate processing results cannot be stored in the buffer RAM with certainty.
Thus, since the processor executes convolution processing at the video rate of 167 ns, there is a limitation with read/write control of a RAM having an access time of 50 ns. In order to avoid this read/write temporal limitation, the conventional apparatus is so adapted that the convolution processing is executed in twice the period, i.e., at a time equivalent to 2.times.T. As a result, picture processing cannot be increased.